Standard FLASH memory devices comprise an array of one-bit storage cells, wherein each memory cell may assume two possible states that correspond to the two logic states (‘1’ or ‘0’) of a bit. The two logic states are associated to different electric charges stored in a floating gate of the cell, that is, to different threshold voltages of the cell.
Typically, a programmed cell (logic value ‘0’) has a higher threshold voltage than an erased cell (logic value ‘1’). Because of the statistical spread due to multiple causes, actual threshold voltages of erased cells and programmed cells of a memory sector typically have a statistical distribution generally as the one depicted in FIG. 1.
Multi-level memory devices are based on cells capable of assuming more than two logic states, and thus may store information for more than one bit. In a four-level memory, each cell is capable of storing two bits of information by fixing its threshold voltage according to the statistical distribution depicted in FIG. 2.
The state ‘11’ is stored by performing an erase operation, the other three states (‘10’, ‘01’ and ‘00’) are obtained by performing a program operation. The more accurate the erase and program operations, the less dispersed the distributions of states ‘11’, ‘10’, ‘01’ and ‘00’ around the respective mean values.
An advantage of a two-bit-per-cell memory device may be the reduction of silicon area used compared to a one-bit-per-cell memory device of identical storage capacity. However, the program and read operations are more complex since the two-bit-per-cell memory device manages a larger number of threshold voltage levels for each cell. The precision with which read operations are carried out determines the amplitude of the applied separation interval ΔREAD between two adjacent threshold distributions, such that, the read operation may be reliably carried out. FIG. 3 depicts such a separation interval and the amplitudes ΔERASE and ΔPROGRAM of the distributions of the threshold voltages.
There are two phenomena that may determine a minimum internal amplitude of the interval in which the threshold voltage of memory cells is defined: the “read disturb” for the lower bound, and the “retention” for the upper bound. The “read disturb” phenomenon, due to repeated read operations that are carried out on the device, raises (FIG. 4) the threshold voltage of low threshold voltage cells bringing them to change from this proper state of erased cells (‘11’) to behave as programmed cells (‘10’). The “retention” phenomenon causes the loss of charge in the cells of high threshold (‘00’), thus cells programmed to the state ‘00’ tend to become cells programmed to the state ‘01’, as also depicted in FIG. 4.
For a certain precision of read, program, and erase operations of the memory device, there may be an upper limit to the number different threshold distributions that may be implemented without “read disturb” and “retention” causing loss of information. Both phenomena are enhanced with the reduction of the size of the cells, thus there is a technological limit beyond which it becomes impossible to realize a two-bit-per-cell memory device of acceptable reliability.
In an attempt to address these limitations, an error correction code (ECC) is used by reserving memory cells, commonly called correction cells, the content of which is determined as a function of the data stored in the cells of the array to be able to correct eventual loss of information. For example, in NOR FLASH memory devices in which a page of data, typically comprising 4, 8, or 16 words, is read at one time, for each page, there is a certain number k of correction cells: the larger the value of k, the larger the number of bits that can be corrected on a same page.
A drawback of this approach is the addition of memory cells for ECC increases the silicon area occupied with respect to a standard multi-level memory of the same size (even if silicon area occupation remains smaller than a one-bit-per-cell memory device). Another drawback may be that the ECC limits the operations that may be executed by users. In a NOR FLASH memory device, it is possible to carry out the program operation on a single cell, but the erase operation may be executed in parallel on all the cells of a sector. The presence of cells for storing the ECC bit may not allow users to carry out a program operation on each page without erasing the whole memory sector. Indeed, a program operation (1→0) may imply erasing (0→1) for at least a correction cell. As stated hereinbefore, this may not be done on a single cell of a NOR FLASH memory device, but only on the whole addressed sector to which the cell belongs. As a consequence, the use of ECCs in NOR FLASH memory devices may limit the so-called “bit manipulation”, i.e. the possibility of programming single bits of the memory.